One critical self-timed delay in memory devices such as dynamic random-access memory (DRAM) devices is the delay between activation of word lines and setting of the corresponding sense amplifiers. As discussed in detail herein, an ideal set delay for a constant voltage word system would be a delay which increases slightly with supply voltage VDD to the memory device. Briefly explained, this is because in a complementary metal-oxide semiconductor (CMOS) array with a constant word line voltage architecture the word line high level V.sub.WL is set independent of supply voltage VDD, whereas the conventional bit line precharge voltage of VDD/2 obviously varies with supply voltage VDD. Thus, the minimal word line voltage, and hence the word line rise time, necessary to transfer a "1" level to a bit line increases with supply voltage VDD. The delay between word line activation and sense amplifier setting would therefore also preferably increase with increasing supply voltage VDD.
Previously, conventional gate delay chains have been employed to generate on-chip clocking delays. Unfortunately, the "trip point" of such a chain increases linearly with supply voltage VDD, while the current drive of the previous stage increases with the square of supply voltage VDD. Hence, the delay length generated by the delay chain decreases as supply voltage VDD increases. Furthermore, inverter-based clocking signals typically vary as a function of process and temperature. Therefore, in order to guarantee sufficient delay at high voltage conditions, and other operating extremes, extra delay must be added to the inverter chain. This extra delay necessarily degrades performance of the semiconductor memory device.
An alternative clocking approach is presented by Watanabe et al. in an article entitled "A New CR-Delay Circuit Technology For High Density and High Speed DRAMs", IEEE Journal of Solid-State Circuits, Vol. 24, No. 4, pp. 905-910, August 1989. In this technique, a resistance-capacitance (RC) time constant is employed by measuring the time taken to discharge a capacitor to a certain percentage of supply voltage VDD. The RC time constant is independent of supply voltage VDD, depending only on the absolute value of the resistor and the capacitor in the network. Although good process control over the capacitance and resistance elements is claimed, in practice there is a twenty (20%) percent variation in the gate capacitance and a 2.times. variation in the n-well capacitance (i.e., the resistive element). Thus, the RC of this circuit necessarily has a large process dependence. Furthermore, in a constant boost voltage architecture, a supply voltage VDD independent clocking delay is not ideal.